Proper Weyl Collineations in Kantowski-Sachs and Bianchi Type III Space-Times

A study of proper Weyl collineations in Kantowski-Sachs and Bianchi type III space-times is given by using the rank of the 6X6 Weyl matrix and direct integration techniques. Studying proper Weyl collineations in each of the above space-times, it is shown that there exists no such possibility when the above space-times admit proper Weyl collineations.Comment: 5 page

Symmetries of the Weyl tensor in Bianchi V spacetimes

Symmetries of geometrical and physical quantities in general relativity provide important information about the curvature structure of the spacetimes. Symmetries of the curvature and the Weyl tensors, known as curvature and Weyl collineations respectively, are two of such important symmetries. Some results on these symmetries for Bianchi type V spacetimes are discussed.Comment: 4 pages; Proc. 11th Marcel Grossmann Meeting on General Relativity, World Scientific, 200

Proper projective collineation in non-static spherically symmetric space-times

We investigate the proper projective collineation in non-static spherically symmetric space-times using direct integration and algebraic techniques. Studying projective collineation in the above space-times, it is shown that the space-times which admit proper projective collineations turn out to be very special classes of static spherically symmetric space-times.Comment: 13 page

Predictable multi-processor system on chip design for multimedia applications

The design of multimedia systems has become increasingly complex due to consumer requirements. Consumers demand the functionalities offered by a huge desktop from these systems. Many of these systems are mobile. Therefore, power consumption and size of these devices should be small. These systems are increasingly becoming multi-processor based (MPSoCs) for the reasons of power and performance. Applications execute on these systems in different combinations also known as use-cases. Applications may have different performance requirements in each use-case. Currently, verification of all these use-cases takes bulk of the design effort. There is a need for analysis based techniques so that the platforms have a predictable behaviour and in turn provide guarantees on performance without expending precious man hours on verification. In this dissertation, techniques and architectures have been developed to design and manage these multi-processor based systems efficiently. The dissertation presents predictable architectural components for MPSoCs, a Predictable MPSoC design strategy, automatic platform synthesis tool, a run-time system and an MPSoC simulation technique. The introduction of predictability helps in rapid design of MPSoC platforms. Chapter 1 of the thesis studies the trends in modern multimedia applications and processor architectures. The chapter further highlights the problems in the design of MPSoC platforms and emphasizes the need of predictable design techniques. Predictable design techniques require predictable application and architectural components. The chapter further elaborates on Synchronous Data Flow Graphs which are used to model the applications throughout this thesis. The chapter presents the architecture template used in this thesis and enlists the contributions of the thesis. One of the contributions of this thesis is the design of a predictable component called communication assist. Chapter 2 of the thesis describes the architecture of this communication assist. The communication assist presented in this thesis not only decouples the communication from computation but also provides timing guarantees. Based on this communication assist, an MPSoC platform generation technique has been presented that can design MPSoC platforms capable of satisfying the throughput constraints of multiple applications in all use-cases. The technique is presented in Chapter 3. The design strategy uses three simple steps for platform design. In the first step it finds the required number of processors. The second step minimizes the communication interconnect between the processors and the third step minimizes the communication memory requirement of the platform. Further in Chapter 4, a tool has been developed to generate CA-based platforms for FPGAs. The output of this tool can be used to synthesize platforms on real hardware with the help of FPGA synthesis tools. The applications executing on these platforms often exhibit dynamism e.g. variation in task execution times and change in application throughput requirements. Further, new applications may often be added by consumers at run-time. Resource managers have been presented in literature to handle such dynamic situations. However, the scalability of these resource managers becomes an issue with the increase in number of processors and applications. Chapter 5 presents distributed run-time resource management techniques. Two versions of distributed resource managers have been presented which are scalable with the number of applications and processors. MPSoC platforms for real-time applications are designed assuming worst-case task execution times. It is known that the difference between average-case and worst-case behaviour can be quite large. Therefore, knowing the average case performance is also important for the system designer, and software simulation is often employed to estimate this. However, simulation in software is slow and does not scale with the number of applications and processing elements. In Chapter 6, a fast and scalable simulation methodology is introduced that can simulate the execution of multiple applications on an MPSoC platform. It is based on parallel execution of SDF (Synchronous Data Flow) models of applications. The simulation methodology uses Parallel Discrete Event Simulation (PDES) primitives and it is termed as "Smart Conservative PDES". The methodology generates a parallel simulator which is synthesizable on FPGAs. The framework can also be used to model dynamic arbitration policies which are difficult to analyse using models. The generated platform is also useful in carrying out Design Space Exploration as shown in the thesis. Finally, Chapter 7 summarizes the main findings and (practical) implications of the studies described in previous chapters of this dissertation. Using the contributions mentioned in the thesis, a designer can design and implement predictable multiprocessor based systems capable of satisfying throughput constraints of multiple applications in given set of use-cases, and employ resource management strategies to deal with dynamism in the applications. The chapter also describes the main limitations of this dissertation and makes suggestions for future research

Fault-tolerant Designs in Lattice Networks on the Klein Bottle

In this note, we consider triangular, square and hexagonal lattices on the flat Klein bottle, and find subgraphs with the property that for any $j$ vertices there exists a longest path (cycle) avoiding all of them. This completes work previously done in other lattices

Brittle fracture of polymer transient networks

We study the fracture of reversible double transient networks, constituted of water suspensions of entangled surfactant wormlike micelles reversibly linked by various amounts of telechelic polymers. We provide a state diagram that delineates the regime of fracture without necking of the filament from the regime where no fracture or break-up has been observed. We show that filaments fracture when stretched at a rate larger than the inverse of the slowest relaxation time of the networks. We quantitatively demonstrate that dissipation processes are not relevant in our experimental conditions and that, depending on the density of nodes in the networks, fracture occurs in the linear viscoelastic regime or in a non-linear regime. In addition, analysis of the crack opening profiles indicates deviations from a parabolic shape close to the crack tip for weakly connected networks. We demonstrate a direct correlation between the amplitude of the deviation from the parabolic shape and the amount of non linear viscoelasticity